Memory apparatus having hierarchical error correction code layer
US10853167B2 · kind B2 · utility
1Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Apr 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N−1 pre-set error correction number(s), and N is a positive integer larger than 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.