Patent · US Active

System architecture with query based address translation for access validation

US10853271B2 · kind B2 · utility

1Cited by

2References

21Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Tessil Thomas · Bengaluru, IN
Jamshed Jalal · Austin, US
Andrea Pellegrini · Trento, IT
Anitha Kona · Austin, US

Key dates

Filing date	Aug 3, 2018
Grant date	Dec 1, 2020
Priority date	—
Expiry date	Jan 24, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.