Tessil Thomas
51Patents
9h-index
80Co-inventors
77Inventor score
Filing activity: Jun 30, 2005 → Mar 23, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7600078B1 | Speculatively performing read transactions | Physics | 114 | Active |
| US7756053B2 | Memory agent with error hardware | Physics | 94 | Active |
| US9342453B2 | Memory channel that supports near memory and far memory access | Emerging Cross-Sectional Technologies | 77 | Active |
| US7913147B2 | Method and apparatus for scrubbing memory | Physics | 55 | Active |
| US9619408B2 | Memory channel that supports near memory and far memory access | Emerging Cross-Sectional Technologies | 30 | Active |
| US7987352B2 | Booting with sub socket partitioning | Physics | 19 | Active |
| US10241943B2 | Memory channel that supports near memory and far memory access | Emerging Cross-Sectional Technologies | 18 | Active |
| US10282323B2 | Memory channel that supports near memory and far memory access | Emerging Cross-Sectional Technologies | 14 | Active |
| US10282322B2 | Memory channel that supports near memory and far memory access | Emerging Cross-Sectional Technologies | 14 | Active |
| US7475314B2 | Mechanism for read-only memory built-in self-test | Physics | 7 | Active |
| US8892924B2 | Reducing power consumption of uncore circuitry of a processor | Emerging Cross-Sectional Technologies | 4 | Active |
| US10359831B2 | Cache power management | Emerging Cross-Sectional Technologies | 4 | Active |
| US8635380B2 | Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning | Physics | 4 | Active |
| US10846250B2 | Apparatus and method for handling address decoding in a system-on-chip | Physics | 3 | Active |
| US9052899B2 | Idle power reduction for memory subsystems | Emerging Cross-Sectional Technologies | 3 | Active |
| US8892929B2 | Reducing power consumption of uncore circuitry of a processor | Emerging Cross-Sectional Technologies | 3 | Active |
| US7730246B2 | Opportunistic transmission of software state information within a link based computing system | Physics | 2 | Active |
| US8745464B2 | Rank-specific cyclic redundancy check | Electricity | 2 | Active |
| US8296522B2 | Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning | Physics | 2 | Active |
| US8527836B2 | Rank-specific cyclic redundancy check | Electricity | 2 | Active |
| US9122780B2 | Monitoring resource usage by a virtual machine | Physics | 1 | Active |
| US10133341B2 | Delegating component power control | Emerging Cross-Sectional Technologies | 1 | Active |
| US10853271B2 | System architecture with query based address translation for access validation | Physics | 1 | Active |
| US8151081B2 | Method, system and apparatus for memory address mapping for sub-socket partitioning | Physics | 1 | Active |
| US10025686B2 | Generating and communicating platform event digests from a processor of a system | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.