Patent · US Active

Fuse-based logic repair

US10853542B1 · kind B1 · utility

3Cited by

5References

20Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Samit Sengupta · San Jose, US
Anil Chowdary Kota · San Diego, US
Fadoua CHAFIK · San Diego, US

Key dates

Filing date	Jun 14, 2019
Grant date	Dec 1, 2020
Priority date	—
Expiry date	Jun 14, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2117/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.