Samit Sengupta
22Patents
9h-index
28Co-inventors
75Inventor score
Filing activity: Jun 10, 1997 → Jun 14, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5915203A | Method for producing deep submicron interconnect vias | Electricity | 65 | Expired |
| US6933869B1 | Integrated circuits with temperature-change and threshold-voltage drift compensation | Physics | 29 | Expired |
| US6057587A | Semiconductor device with anti-reflective structure | Electricity | 19 | Expired |
| US6176983A | Methods of forming a semiconductor device | Electricity | 19 | Expired |
| US6255226A | Optimized metal etch process to enable the use of aluminum plugs | Electricity | 15 | Expired |
| US6433433B1 | Semiconductor device with misaligned via hole | Electricity | 13 | Expired |
| US7286020B1 | Techniques for monitoring and replacing circuits to maintain high performance | Electricity | 12 | Expired |
| US6410421B1 | Semiconductor device with anti-reflective structure and methods of manufacture | Electricity | 12 | Expired |
| US6146996A | Semiconductor device with conductive via and method of making same | Electricity | 9 | Expired |
| US6207565A | Integrated process for ashing resist and treating silicon after masked spacer etch | Electricity | 8 | Expired |
| US7468617B1 | Electrostatic discharge (ESD) protection device for use with multiple I/O standards | Electricity | 7 | Active |
| US6162586A | Method for substantially preventing footings in chemically amplified deep ultra violet photoresist layers | Electricity | 6 | Expired |
| US6228757A | Process for forming metal interconnects with reduced or eliminated metal recess in vias | Electricity | 6 | Expired |
| US6235609A | Method for forming isolation areas with improved isolation oxide | Electricity | 6 | Expired |
| US6459153B1 | Compositions for improving interconnect metallization performance in integrated circuits | Electricity | 5 | Expired |
| US6413152B1 | Apparatus for performing chemical-mechanical planarization with improved process window, process flexibility and cost | Performing Operations; Transporting | 4 | Expired |
| US8217457B1 | Electrostatic discharge (ESD) protection device for use with multiple I/O standards | Electricity | 3 | Active |
| US10853542B1 | Fuse-based logic repair | Physics | 3 | Active |
| US10490558B2 | Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells | Electricity | 2 | Active |
| US9076775B2 | System and method of varying gate lengths of multiple cores | Electricity | 0 | Active |
| US9461040B2 | System and method of varying gate lengths of multiple cores | Electricity | 0 | Active |
| US9245971B2 | Semiconductor device having high mobility channel | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.