Operating method of a low current electrically erasable programmable read only memory (EEPROM) array
US10854297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2020 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.