Apparatus and methods for seeding operations concurrently with data line set operations
US10854304B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Dec 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a first string of series-connected memory cells selectively connected to a first data line, applying a first voltage level to the access line for a second memory cell of the first string, applying a second voltage level higher than the first voltage level to the access line for the particular memory cell, applying a third voltage level to the first data line concurrently with applying the first voltage level and concurrently with applying the second voltage level, and applying a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells concurrently with applying the third voltage level to the first data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.