Semiconductor vertical wire bonding structure and method
US10854476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor IC structure having vertical wire bonding and method of making it. The method includes two steps. First step: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on its surface, disposing a wire bonding pad at the first solder joint, to connect to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint. Second step: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.