Diffused bitline replacement in stacked wafer memory
US10854578B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Mar 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.