Invensas LLC
549Patents
546Active
549Granted
62Portfolio score
Filing activity: Oct 26, 2006 → Aug 23, 2022 · 23 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9165793B1 | Making electrical components in handle wafers of integrated circuit packages | Electricity | 311 | Active |
| US9824974B2 | Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies | Electricity | 176 | Active |
| US9741620B2 | Structures and methods for reliable packages | Electricity | 165 | Active |
| US10446456B2 | Integrated circuits protected by substrates with cavities, and methods of manufacture | Electricity | 152 | Active |
| US9899442B2 | Image sensor device | Electricity | 134 | Active |
| US11329034B2 | Direct-bonded LED structure contacts and substrate contacts | Electricity | 124 | Active |
| US11264357B1 | Mixed exposure for large die | Electricity | 123 | Active |
| US10854578B2 | Diffused bitline replacement in stacked wafer memory | Electricity | 123 | Active |
| US10892246B2 | Structures and methods for low temperature bonding using nanoparticles | Electricity | 123 | Active |
| US11355443B2 | Dielets on flexible and stretchable packaging for microelectronics | Electricity | 123 | Active |
| US10840135B2 | Flat metal features for microelectronics applications | Electricity | 122 | Active |
| US8878353B2 | Structure for microelectronic packaging with bond elements to encapsulation surface | Emerging Cross-Sectional Technologies | 122 | Active |
| US8372741B1 | Method for package-on-package assembly with wire bonds to encapsulation surface | Electricity | 95 | Active |
| US8404520B1 | Package-on-package assembly with wire bond vias | Emerging Cross-Sectional Technologies | 93 | Active |
| US11069734B2 | Image sensor device | Electricity | 88 | Active |
| US8680684B2 | Stackable microelectronic package structures | Electricity | 87 | Active |
| US8836136B2 | Package-on-package assembly with wire bond vias | Emerging Cross-Sectional Technologies | 82 | Active |
| US8670261B2 | Stub minimization using duplicate sets of signal terminals | Electricity | 72 | Active |
| US9379074B2 | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects | Electricity | 70 | Active |
| US9812185B2 | DRAM adjacent row disturb mitigation | Physics | 66 | Active |
| US9095074B2 | Structure for microelectronic packaging with bond elements to encapsulation surface | Emerging Cross-Sectional Technologies | 66 | Active |
| US8299368B2 | Interconnection element for electric circuits | Electricity | 66 | Active |
| US9263394B2 | Multiple bond via arrays of different wire heights on a same substrate | Electricity | 62 | Active |
| US9105483B2 | Package-on-package assembly with wire bond vias | Emerging Cross-Sectional Technologies | 62 | Active |
| US9666559B2 | Multichip modules and methods of fabrication | Electricity | 61 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.