Edge based partial response equalization
US10855496B2 · kind B2 · utility
2Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2018 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.