Multiple memory die techniques

US10860417B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Wolfgang Anton Spirkl · Germering, DE
• Thomas Hein · Hersbruck, DE
• Peter Mayer · Neubiberg, DE
• Michael Richter · Ottobrunn, DE
• Martin Brox · Munich, DE

Key dates

• Filing date: Aug 2, 2019
• Grant date: Dec 8, 2020
• Expiry date: Aug 2, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/108
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Methods, systems, and devices for multiple memory die techniques are described. A memory device may include multiple memory dies and may be configured to communicate with a host device. For example, each memory die may be coupled with a set of data pins that includes respective subsets of data pins (e.g., a set of eight data pins having two subsets of four data pins). Further, each memory die may have one or more auxiliary pins used for channel coding information for data communicated over one or more of the subsets of data pins. In some cases, each memory die may include one or more additional auxiliary pins, which may be used for channel coding information for a respective subset of data pins or multiple subsets of data pins. The channel coding information associated with the auxiliary pin(s) may include error detection code information, data coding information, or any combination thereof.