Patent · US Active

Byte select cache compression

US10860489B2 · kind B2 · utility

2Cited by

4References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Shomit N. Das · Austin, US
Matthew Tomei · Champaign, US
David A. Wood · Austin, US

Key dates

Filing date	Oct 31, 2018
Grant date	Dec 8, 2020
Priority date	—
Expiry date	Dec 7, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/401
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.