Semiconductor memory device for resetting counter synchronized with data clock by using reset signal synchronized with system clock and method for operating the same
US10861515B2 · kind B2 · utility
1Cited by
2References
20Claims
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Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.