Distributed memory repair network
US10861578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Dec 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.