Dummy die placement without backside chipping

US10861799B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chih-Wei Wu · Sanxing, TW
• Li-Chung Kuo · Taipei, TW
• Pu Wang · Cambridge, US
• Ying-Ching Shih · Taipei, TW
• Szu-Wei Lu · Baoshan, TW
• Kung-Chen Yeh · Taichung, TW

Key dates

• Filing date: May 17, 2019
• Grant date: Dec 8, 2020
• Expiry date: May 17, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.