Shielding structures
US10861810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Apr 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.