Methods for forming structurally-reinforced semiconductor plug in three-dimensional memory device
US10861868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2018 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Oct 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices with a structurally-reinforced semiconductor plug and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack is formed on a substrate. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. An opening extending vertically through the dielectric stack is formed. A shallow recess is formed by removing a part of a sacrificial layer abutting a sidewall of the opening. The sacrificial layer is at a lower portion of the dielectric stack. A semiconductor plug is formed at a lower portion of the opening. A part of the semiconductor plug protrudes into the shallow recess. A channel structure is formed above and in contact with the semiconductor plug in the opening. A memory stack including a plurality of conductor/dielectric layer pairs is formed by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.