Three-dimensional semiconductor memory devices
US10861876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Apr 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.