Semiconductor structure and manufacturing method of the same

US10862023B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Tai-Yen Peng · Hsinchu, TW
• Yu-Shu Chen
• Chien-Chung Huang · Tainan, TW
• Sin-Yi Yang · Taichung, TW
• Chen-Jung Wang · Hsinchu, TW
• Han-Ting Lin · Hsinchu, TW
• Jyu-Horng Shieh · Hsinchu, TW
• Qiang Fu · Beijing, CN

Key dates

• Filing date: Jan 8, 2019
• Grant date: Dec 8, 2020
• Expiry date: Jan 11, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85

Abstract

The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.