Memory device

US10862026B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Jung-Tang Wu · Kaohsiung, TW
• Szu-Ping Tung · Taipei, TW
• Szu-Hua Wu · Zhubeikou, TW
• Shing-Chyang Pan · Guoxing Township, TW
• Meng-Yu Wu · Taichung, TW

Key dates

• Filing date: Jan 13, 2020
• Grant date: Dec 8, 2020
• Expiry date: Jan 13, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80

Abstract

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.