Methods and apparatus for performing design for debug via protocol interface
US10866278B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test system is provided for performing design for debug (DFD) operations. The test system includes a host processor coupled to an auxiliary device. The auxiliary device includes a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary device further includes a circuit under test (CUT) and a hardened DFD hub that is controlled by the host processor via the protocol interface block. The DFD hub includes a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor directs the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub is fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.