Philippe Molson
25Patents
8h-index
16Co-inventors
68Inventor score
Filing activity: Aug 31, 2000 → Mar 28, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6634009B1 | Interleaver-deinterleaver megacore | Physics | 44 | Expired |
| US7143368B1 | DSP design system level power estimation | Physics | 38 | Expired |
| US7991606B1 | Embedded logic analyzer functionality for system level environments | Physics | 15 | Active |
| US7318014B1 | Bit accurate hardware simulation in system level simulators | Physics | 13 | Expired |
| US7089173B1 | Hardware opencore evaluation | Physics | 11 | Expired |
| US7873953B1 | High-level language code sequence optimization for implementing programmable chip designs | Physics | 11 | Active |
| US9684615B1 | Apparatus and methods for multiple-channel direct memory access | Physics | 10 | Active |
| US7480603B1 | Finite impulse response (FIR) filter compiler | Electricity | 9 | Active |
| US7360189B1 | Method and apparatus for enabling waveform display in a system design model | Physics | 8 | Expired |
| US7509246B1 | System level simulation models for hardware modules | Physics | 8 | Expired |
| US7882457B1 | DSP design system level power estimation | Physics | 7 | Active |
| US9552323B1 | High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry | Physics | 7 | Active |
| US8291396B1 | Scheduling optimization of aliased pointers for implementation on programmable chips | Physics | 6 | Active |
| US7181384B1 | Method and apparatus for simulating a hybrid system with registered and concurrent nodes | Physics | 6 | Expired |
| US7110927B1 | Finite impulse response (FIR) filter compiler | Physics | 6 | Expired |
| US9257987B1 | Partial reconfiguration using configuration transaction layer packets | Electricity | 6 | Active |
| US7676355B1 | Method and apparatus for providing protected intellectual property | Physics | 5 | Active |
| US9053093B1 | Modular direct memory access system | Physics | 3 | Active |
| US8578356B1 | High-level language code sequence optimization for implementing programmable chip designs | Physics | 2 | Active |
| US8661396B1 | DSP design system level power estimation | Physics | 1 | Active |
| US8402419B1 | DSP design system level power estimation | Physics | 1 | Active |
| US8200472B1 | Method and apparatus for providing protected intellectual property | Physics | 1 | Active |
| US9329847B1 | High-level language code sequence optimization for implementing programmable chip designs | Physics | 0 | Active |
| US7865347B1 | Finite impulse response (FIR) filter compiler for estimating cost of implementing a filter | Electricity | 0 | Active |
| US10866278B2 | Methods and apparatus for performing design for debug via protocol interface | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.