Two stage command buffers to overlap IOMMU map and second tier memory reads
US10866755B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Apr 2, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Apr 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.