Monish Shah
30Patents
7h-index
31Co-inventors
69Inventor score
Filing activity: Aug 18, 1987 → Mar 14, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5222205A | Method for generating addresses to textured graphics primitives stored in rip maps | Physics | 117 | Expired |
| US5170468A | Graphics system with shadow ram update to the color map | Physics | 81 | Expired |
| US9436595B1 | Use of application data and garbage-collected data to improve write efficiency of a data storage device | Physics | 73 | Active |
| US5821950A | Computer graphics system utilizing parallel processing for enhanced performance | Physics | 54 | Expired |
| US4958302A | Graphics frame buffer with pixel serializing group rotator | Physics | 21 | Expired |
| US10482009B1 | Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device | Physics | 9 | Active |
| US6279081A | System and method for performing memory fetches for an ATM card | Physics | 7 | Expired |
| US6108721A | Method and apparatus for ensuring data consistency between an i/o channel and a processor | Physics | 7 | Expired |
| US9940230B2 | Compression and decompression of data at high speed in solid state storage | Physics | 5 | Active |
| US11150825B2 | Adaptive spare block usage in solid state drives | Physics | 3 | Active |
| US10459847B1 | Non-volatile memory device application programming interface | Physics | 3 | Active |
| US11455239B1 | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system | Physics | 3 | Active |
| US7035981B1 | Asynchronous input/output cache having reduced latency | Physics | 1 | Expired |
| US10296256B2 | Two stage command buffers to overlap IOMMU map and second tier memory reads | Physics | 1 | Active |
| US10866755B2 | Two stage command buffers to overlap IOMMU map and second tier memory reads | Physics | 0 | Active |
| US11656981B2 | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system | Physics | 0 | Active |
| US11726909B2 | Two-way interleaving in a three-rank environment | Physics | 0 | Active |
| US10942849B2 | Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device | Physics | 0 | Active |
| US9880778B2 | Memory devices and methods | Physics | 0 | Active |
| US12056372B2 | Collecting quality of service statistics for in-use child physical functions of multiple physical function non-volatile memory devices | Physics | 0 | Active |
| US11640334B2 | Error rates for memory with built in error correction and detection | Physics | 0 | Active |
| US5706420A | Super pipelined speculative execution vector generator | Physics | 0 | Expired |
| US11429523B2 | Two-way interleaving in a three-rank environment | Physics | 0 | Active |
| US12079084B2 | Distributed raid for parity-based flash storage devices | Physics | 0 | Active |
| US11775442B2 | Memory system with a predictable read latency from media with a long write latency | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.