Memory system with parity cache scheme and method of operating such memory system
US10866764B2 · kind B2 · utility
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Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a memory system, architecture and operations for processing commands in a parity cache scheme support more open blocks taking into account cost and performance. Dynamic random access memory space holds parity buffers of all open blocks and communicates with a cache and cache controller. An open block queue (OBQ) accumulates commands in separate queues for each open block to increase cache hit rate. Open block counters keep track of the number of commands for each OBQ to facilitate arbitration. A unique identification (ID) is given for each open block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.