Apparatus, method, and system for ensuring quality of service for multi-threading processor cores
US10866834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L41/5025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.