Memory systems having reduced memory channel traffic and methods for operating the same
US10866858B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Apr 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes a nonvolatile memory (NVM) device having a plurality of memory blocks and a control circuit configured to perform a read for copy-back operation in response to a receipt of a corresponding command. The control circuit performs the read for copy-back operation by reading page data from a source memory block of the plurality, generating a syndrome from the read page data, outputting the syndrome, receiving error location data in response to outputting the syndrome, correcting the read page data using the received error location data, and writing the corrected read page data to a target memory block among the plurality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.