Patent · US Active

Area efficient write data path circuit for SRAM yield enhancement

US10867668B2 · kind B2 · utility

1Cited by

3References

32Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Sharad Gupta · New Delhi, IN
Pradeep Raj · Atrauli, IN
Rahul Sahu · Kanchinakote, IN
Mukund Narasimhan · Bengaluru, IN

Key dates

Filing date	Oct 6, 2017
Grant date	Dec 15, 2020
Priority date	—
Expiry date	Oct 6, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.