Pradeep Raj
14Patents
4h-index
20Co-inventors
52Inventor score
Filing activity: Mar 31, 2015 → Mar 12, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9865337B1 | Write data path to reduce charge leakage of negative boost | Physics | 13 | Active |
| US10811088B2 | Access assist with wordline adjustment with tracking cell | Physics | 5 | Active |
| US9721650B1 | Architecture to improve write-ability in SRAM | Physics | 5 | Active |
| US11049552B1 | Write assist circuitry for memory | Physics | 4 | Active |
| US9916892B1 | Write driver circuitry to reduce leakage of negative boost charge | Physics | 2 | Active |
| US10867668B2 | Area efficient write data path circuit for SRAM yield enhancement | Physics | 1 | Active |
| US10811086B1 | SRAM write yield enhancement with pull-up strength modulation | Physics | 1 | Active |
| US11955169B2 | High-speed multi-port memory supporting collision | Physics | 1 | Active |
| US9478278B1 | Read-write contention circuitry | Physics | 0 | Active |
| US12183393B2 | High-speed multi-port memory supporting collision | Physics | 0 | Active |
| US12020766B2 | Memory circuit architecture with multiplexing between memory banks | Physics | 0 | Active |
| US12020746B2 | Memory write assist with reduced switching power | Physics | 0 | Active |
| US12047073B2 | Power supply circuit with reduced leakage current | Emerging Cross-Sectional Technologies | 0 | Active |
| US11837313B2 | Memory with efficient DVS controlled by asynchronous inputs | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.