SRAM memory having subarrays with common IO block
US10867681B2 · kind B2 · utility
7Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.