Michael Patrick Clinton
29Patents
11h-index
29Co-inventors
75Inventor score
Filing activity: Dec 6, 1993 → Jun 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8508974B2 | Ferroelectric memory with shunt device | Physics | 58 | Active |
| US8717800B2 | Method and apparatus pertaining to a ferroelectric random access memory | Physics | 57 | Active |
| US5412613A | Memory device having asymmetrical CAS to data input/output mapping and applications thereof | Physics | 23 | Expired |
| US7733686B2 | Pulse width control for read and write assist for SRAM circuits | Physics | 22 | Active |
| US6330697A | Apparatus and method for performing a defect leakage screen test for memory devices | Physics | 18 | Expired |
| US7936624B2 | Reduced power bitline precharge scheme for low power applications in memory devices | Physics | 16 | Active |
| US9236113B2 | Read assist for an SRAM using a word line suppression circuit | Physics | 15 | Active |
| US8755239B2 | Read assist circuit for an SRAM | Physics | 15 | Active |
| US7864600B2 | Memory cell employing reduced voltage | Physics | 13 | Active |
| US8248867B2 | Memory cell employing reduced voltage | Physics | 11 | Active |
| US8477522B2 | Ferroelectric memory write-back | Physics | 11 | Active |
| US8437214B2 | Memory cell employing reduced voltage | Physics | 10 | Active |
| US8379465B2 | Combined write assist and retain-till-accessed memory array bias | Physics | 10 | Active |
| US9082507B2 | Read assist circuit for an SRAM, including a word line suppression circuit | Physics | 10 | Active |
| US7512030B2 | Memory with low power mode for WRITE | Physics | 9 | Active |
| US5898623A | Input port switching protocol for a random access memory | Physics | 7 | Expired |
| US10867681B2 | SRAM memory having subarrays with common IO block | Physics | 7 | Active |
| US5969997A | Narrow data width DRAM with low latency page-hit operations | Physics | 4 | Expired |
| US7671663B2 | Tunable voltage controller for a sub-circuit and method of operating the same | Physics | 4 | Active |
| US8331187B2 | Memory with low power mode for write | Physics | 3 | Active |
| US8995164B2 | High-performance scalable read-only-memory cell | Electricity | 2 | Active |
| US8756558B2 | FRAM compiler and layout | Physics | 2 | Active |
| US7974144B2 | Memory with tunable sleep diodes | Physics | 1 | Active |
| US8724367B2 | Method and apparatus pertaining to a ferroelectric random access memory | Physics | 1 | Active |
| US11393514B2 | Turbo mode SRAM for high performance | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.