Wafer stack and fabrication method thereof
US10867836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2016 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jul 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.