Interconnect chips
US10867954B2 · kind B2 · utility
5Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19104
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.