Memory devices, cross-point memory arrays and methods of fabricating a memory device
US10868081B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.