Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) circuit for transceivers
US10868663B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2020 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/36
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.