Non-volatile memory with selective interleaved coding based on block reliability
US10871910B1 · kind B1 · utility
10Cited by
1References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the disclosure teaches an apparatus including a memory array and a processor in communication with the memory array. The processor is configured to determine health scores of blocks of the memory array, where the health scores indicate the health of the blocks. The processor also is configured to receive data from a host, and select an interleaving scheme for programming the data based on the data type and a block to which the data is written based on the health scores. In one embodiment, sequential type data is written to unhealthy blocks and non-sequential data is written to healthy blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.