Ariel Navon
164Patents
10h-index
63Co-inventors
79Inventor score
Filing activity: Mar 26, 2008 → Jul 1, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8301979B2 | Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders | Electricity | 35 | Active |
| US9947401B1 | Peak current management in non-volatile storage | Physics | 34 | Active |
| US9697905B2 | Updating read voltages using syndrome weight comparisons | Physics | 23 | Active |
| US9135155B2 | Storage and retrieval of shaped data | Physics | 20 | Active |
| US8645810B2 | Fast detection of convergence or divergence in iterative decoding | Electricity | 19 | Active |
| US8720682B2 | Holders for portable memory cards and methods for manufacturing same | Emerging Cross-Sectional Technologies | 15 | Active |
| US9268635B2 | Error correction using multiple data sources | Electricity | 13 | Active |
| US10223199B2 | Non-volatile memory configured to return error reduced read data | Electricity | 12 | Active |
| US11068165B2 | Non-volatile memory data write management | Physics | 10 | Active |
| US9312002B2 | Methods for programming ReRAM devices | Physics | 10 | Active |
| US10871910B1 | Non-volatile memory with selective interleaved coding based on block reliability | Physics | 10 | Active |
| US10866740B2 | System and method for performance-based multiple namespace resource allocation in a memory | Physics | 9 | Active |
| US10250281B2 | ECC decoder having adjustable parameters | Physics | 8 | Active |
| US10289341B2 | Operating parameter offsets in solid state memory devices | Physics | 8 | Active |
| US9583183B2 | Reading resistive random access memory based on leakage current | Physics | 7 | Active |
| US10997080B1 | Method and system for address table cache management based on correlation metric of first logical address and second logical address, wherein the correlation metric is incremented and decremented based on receive order of the first logical address and the second logical address | Physics | 7 | Active |
| US9484089B2 | Dual polarity read operation | Physics | 7 | Active |
| US10712949B2 | Adaptive device quality of service by host memory buffer range | Physics | 7 | Active |
| US10732848B2 | System and method for predictive read of random data | Physics | 6 | Active |
| US10474525B2 | Soft bit techniques for a data storage device | Physics | 6 | Active |
| US10372378B1 | Replacement data buffer pointers | Physics | 6 | Active |
| US10613778B2 | Dynamic host memory allocation to a memory controller | Physics | 6 | Active |
| US11210183B2 | Memory health tracking for differentiated data recovery configurations | Physics | 5 | Active |
| US10180874B2 | Storage device operations based on bit error rate (BER) estimate | Electricity | 5 | Active |
| US11501109B2 | Non-volatile memory die with on-chip data augmentation components for use with machine learning | Physics | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.