Internal error checking and correction (ECC) with extra system bits
US10872011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2017 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jan 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2{circumflex over ( )}N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.