Non volatile memory controller device and method for adjustment
US10872013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.