Remote memory access using memory mapped addressing among multiple compute nodes
US10872056B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.