Partitioning in a compiler flow for a heterogeneous multi-core architecture
US10872057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.