System comprising a memory capable of implementing calculation operations
US10872642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2018 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.