System and method for controlling semiconductor memory device including multiple charge storage regions
US10872900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.