Using inverse lithography technology in a method of mask data preparation for generating integrated circuit
US10877380B1 · kind B1 · utility
8Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 17, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of generating an integrated circuit includes: receiving, by a processor, a first IC design layout; replacing, by the processor, a specific region in the first IC design layout with a first difference region; performing, by the processor, an inverse lithography technology process upon a junction region between the first difference region and the first IC design layout to generate a mask data; and causing the IC to be fabricated according to the mask data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.