Storing cache lines in dedicated cache of an idle core
US10877886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiment of this disclosure provides a mechanism to store cache lines in dedicated cache of an idle core. In one embodiment, a multi-core processor comprising a first core, a second core, a first cache, a second cache, a third cache, and a cache controller unit is provided. The cache controller is operatively coupled to at least the first cache, the second cache, and the third cache. The cache controller is to evict a first line from the first cache, wherein the first core is in an active state. Responsive to the evicting of the first line, the first line is stored in the third cache. Responsive to storing the first line, a second line is evicted from the third cache. Responsive to evicting the second line, the second line is stored in the second cache when the second core is in an idle state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.