Technologies for controlling memory access transactions received from one or more I/O devices
US10878134B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for secure I/O include a compute device, which further includes a processor, a memory, a trusted execution environment (TEE), one or more input/output (I/O) devices, and an I/O subsystem. The I/O subsystem includes a device memory access table (DMAT) programmed by the TEE to establish bindings between the TEE and one or more I/O devices that the TEE trusts and a memory ownership table (MOT) programmed by the TEE when a memory page is allocated to the TEE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.