Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference
US10878153B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Oct 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for performing domain crossing verification of a register transfer level (RTL) representation of an integrated circuit (IC) that includes a memory block are provided. One example method includes receiving an RTL representation of an IC; automatically inferring one or more memory blocks in the RTL representation of the IC; identifying one or more input ports and one or more output ports of the one or more memory blocks; designating the one or more input ports and the one or more output ports as one or more start points and one or more end points; and performing domain crossing analysis on the RTL representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.