Evaluation of nets for suitability of time domain multiplexing during partitioning and placing a circuit design
US10878154B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jul 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed approaches involve evaluating by a design tool executing on a computer system, a plurality of nets of a circuit design for individual levels of suitability for cutting each net into a cut net that crosses a partition boundary between a plurality of partitions of an integrated circuit (IC) device. The design tool partitions the circuit design. The partitioning includes cutting one or more of the nets into cut nets and favoring the cutting of ones of the plurality of nets having a greater level of suitability over others of the plurality of nets having a lesser level of suitability. The design tool assigns each cut net to one group of a plurality of groups and inserts respective time-division multiplexing circuitry on each group of cut nets. The design toon then places the circuit design on the IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.