Method and system for performing analog complex vector-matrix multiplication
US10878317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Mar 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.